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toshiba TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 1 pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin name a 11 a 9 a 8 a 13 r/w ce2 a 15 v dd nc a 16 a 14 a 12 a 7 a 6 a 5 a 4 pin no. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pin name a 3 a 2 a 1 a 0 i/o1 i/o2 i/o3 gnd i/o4 i/o5 i/o6 i/o7 i/o8 ce1 a 10 oe features low power dissipation : 27.5mw/mhz (typ.) standby current: 4 m a (max.) at ta = 25 c 5v single power supply access time (max.) power down feature: ce1 , ce2 data retention supply voltage: 2.0 ~ 5.5v inputs and outputs directly ttl compatible package TC551001bpl : dip32-p-600 TC551001bfl : sop32-p-525 TC551001bftl : tsop32-p-0820 TC551001btrl : tsop32-p-0820a TC551001bpl/bfl/bftl/btrl -70l -85l access time 70ns 85ns ce1 access time 70ns 85ns ce2 access time 70ns 85ns oe access time 35ns 45ns pin connection (top view) tsop pinout silicon gate cmos 131,072 word x 8 bit static ram description the TC551001bpl is a 1,048,576 bits static random access memory organized as 131,072 words by 8 bits using cmos technology, and operated from a single 5v power supply. advanced circuit techniques provide both high speed and low power features with an operating current of 5ma/mhz (typ.) and a minimum cycle time of 70ns. when ce1 is a logical high, or ce2 is low, the device is placed in a low power standby mode in which the standby current is 2 m a typically. the TC551001bpl has three control inputs. chip enable inputs (ce1 , ce2) allow for device selection and data retention control, while an output enable input (oe ) provides fast memory access. the TC551001bpl is suitable for use in microprocessor application systems where high speed, low power, and battery backup are required. the TC551001bpl is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic package, and a thin small outline plastic package (forward, reverse type). pin names a0 ~ a16 address inputs r/w read/write control input oe output enable input ce1 , ce2 chip enable inputs i/o1 ~ i/o8 data input/output v dd power (+5v) gnd ground n.c. no connection
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 2 toshiba america electronic components, inc . block diagram * h or l maximum ratings * -3.0v at pulse width of 50ns max ** sop operating mode operation mode ce1 ce2 oe r/w i/o1 ~ i/o8 power read l h l h d out i ddo write l h * l d in i ddo output deselect l h h h high-z i ddo standby h * * * high-z i dds * l * * high-z i dds symbol item rating unit v dd power supply voltage -0.3 ~ 7.0 v v in input voltage -0.3* ~ 7.0 v v i/o input and output voltage -0.5 ~ v dd + 0.5 v p d power dissipation 1.0/0.6** w t solder soldering temperature (10s) 260 c t strg storage temperature -55 ~ 150 c t opr operating temperature 0 ~ 70 c
sr01020795 static ram TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 3 * -3.0v at pulse width of 50ns max. dc and operating characteristics (ta = 0 ~ 70?, v dd = 5v 10%) note: (1) in standby mode with ce1 3 v dd - 0.2v, these speci?ation limits are guaranteed under the condition of ce2 3 v dd - 0.2v or ce2 0.2v. note: this parameter is periodically sampled and is not 100% tested. dc recommended operating conditions symbol parameter min. typ. max. unit v dd power supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd + 0.3 v il input low voltage -0.3* 0.8 v dh data retention supply voltage 2.0 5.5 symbol parameter test condition min. typ. max. unit i li input leakage current v in = 0 ~ v dd 1.0 m a i lo output leakage current ce1 = v ih or ce2 = v il or r/w = v il or oe = v ih, v out = 0 ~ v dd 1.0 m a i oh output high current v oh = 2.4v -1.0 ma i ol output low current v ol = 0.4v 4.0 ma i ddo1 operating current ce1 = v il and ce2 = v ih and r/w = v ih, i out = 0ma other inputs = v ih /v il t cycle min. 70 ma 1 m s 20 i ddo2 ce1 = 0.2v and ce2 = v dd - 0.2v r/w = v dd - 0.2v i out = 0ma other inputs = v dd - 0.2v/0.2v t cycle min. 60 1 m s 10 i dds1 standby current ce1 = v ih or ce2 = v il 3 ma i dds2 (1) ce1 = v dd - 0.2v or ce2 = 0.2v v dd = 2.0v ~ 5.5v ta = 0 ~ 70 c 30 m a ta = 25 c 2 4 capacitance (ta = 25?, f = 1mhz) symbol parameter test condition max. unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 4 toshiba america electronic components, inc . ac characteristics (ta = 0 ~ 70 c, v dd = 5v 10%) read cycle write cycle ac test conditions symbol parameter TC551001bpl/bfl/bftl/btrl unit -70l -85l min. max. min. max. t rc read cycle time 70 85 ns t acc address access time 70 85 t co1 ce 1 access time 70 85 t co2 ce2 access time 70 85 t oe output enable to output in valid 35 45 t coe chip enable (ce 1 , ce2) to output in low-z 10 10 t oee output enable to output in low-z 5 5 t od chip enable (ce 1 , ce2) to output in high-z 25 30 t odo output enable to output in high-z 25 30 t oh output data hold time 10 10 symbol parameter TC551001bpl/bfl/bftl/btrl unit -70l -85l min. max. min. max. t wc write cycle time 70 85 ns t wp write pulse width 50 60 t cw chip selection to end of write 60 75 t as address setup time 0 0 t wr write recovery time 0 0 t odw r/w to output in high-z 25 30 t oew r/w to output in low-z 5 5 t ds data setup time 30 35 t dh data hold time 0 0 input pulse levels 2.4v/0.6v input pulse rise and fall time 5ns input timing measurement reference level 1.5v output timing measurement reference level 1.5v output load 1 ttl gate and c l = 100pf
sr01020795 static ram TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 5 timing waveforms read cycle (1) write cycle 1 (4) (r/w controlled write)
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 6 toshiba america electronic components, inc . write cycle 2 (4) (ce1 controlled write) write cycle 3 (4) (ce2 controlled write)
sr01020795 static ram TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 7 notes: 1. r/w is high for read cycle. 2. assuming that ce1 low transition or ce2 high transition occurs coincident with or after the r/w low transition, out- puts remain in a high impedance state. 3. assuming that ce1 high transition or ce2 low transition occurs coincident with or prior to the r/w high transition, outputs remain in a high impedance state. 4. assuming that oe is high for a write cycle, outputs are in a high impedance state during this period. 5. the i/o may be in the output state during this time, input signals of opposite phase must not be applied.
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 8 toshiba america electronic components, inc . data retention characteristics (ta = 0 ~ 70 c) *3 m a (max.) ta = 0 ~ 40 c ce1 controlled data retention mode (1) ce2 controlled data retention mode (3) notes: 1. in the ce1 controlled data retention mode, minimum standby current is achieved under the condition ce2 0.2v or ce2 3 v dd - 0.2v. 2. if the v ih of ce1 is 2.2v in operation, during the period that the v dd voltage is going down from 4.5v to 2.4v, i dds1 current ?ws. 3. in the ce2 controlled data retention mode, minimum standby current is achieved under the condition ce2 0.2v. symbol parameter min. typ. max. unit v dh data retention supply voltage 2.0 5.5 v i dds2 standby current v dd = 3.0v 15* m a v dd = 5.5v 30 t cdr chip deselect to data retention mode 0 ns t r recovery time 5 ms
sr01020795 static ram TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 9 outline drawing dip32-p-600 unit in mm
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 10 toshiba america electronic components, inc . outline drawing sop32-p-525 unit in mm
sr01020795 static ram TC551001bpl/bfl/bftl/btrl-70l/85l toshiba america electronic components, inc . 11 outline drawing tsop32-p-0820 unit in mm
TC551001bpl/bfl/bftl/btrl-70l/85l static ram sr01020795 12 toshiba america electronic components, inc . outline drawing tsop32-p-0820a unit in mm 1. this technical data may be controlled under u.s. export administration regulations and may be subject to the approval of the u.s. department of commerce prior to export. any export or re-export, directly or indi- rectly, in contravention of the u.s. export administration regulations is strictly prohibited. 2. life support policy toshiba products described in this document are not authorized for use as critical components in life support systems without the written consent of the appropriate of?er of toshiba america, inc. life support sys- tems are either systems intended for surgical implant in the body or systems which sustain life. a critical component in any component of a life support system whose failure to perform may cause a malfunction of the life support system, or may affect its safety or effectiveness. 3. the information in this document has been carefully checked and is believed to be reliable; however no responsibility can be assumed for inaccuracies that may not have been caught. all information in this data book is subject to change without prior notice. furthermore, toshiba cannot assume responsibility for the use of any license under the patent rights of toshiba or any third parties.
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